We are introducing changes in the cache hardware architecture to avoid the information leakage due to Side-channel attacks.
We are developing ISA extensions as well as reconfigurable accelerators for Deep Learning.
We have been evaluating several optimizations related to memory systems including optimizations for cache memories and heterogenous memory systems. In terms of cache memories, we have investigated separating array structures from other data elements and design separate array and scalar data caches. We have also investigated using different cache indexing techniques to minimize conflicts among multiple applications as well as improve security against cache side-channel attacks.
In terms of heterogeneous memory systems, we investigated using 3D DRAMs as last level cache, as part of main memory and as prefetch buffer to slower memories such as DDR or NVM. We explored different page migration strategies and prefetching strategis.
We explored embedding processing capabilities on the logic layer of a 3D stacked memory. We explored the use of simple in-order RISC (ARM) cores, reconfigurable dataflow graphs and GPUs as processing elements ebedded on the logic layer.
We have been investigating hybrid dataflow—von Neumann architectures for multithreaded systems. We have investigated the use of instruction, data, and I-structure cache memories with ETS dataflow.
We developed an architecture for dataflow known as Scheduled Dataflow (SDF) that executes instructions synchronously.
Learn more about SDF on our Scheduled Dataflow page.
Moola: A multicore cache simulator
Gleipnir: A memory profiling tools