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Processing In Memory

Moving computation closer to memory may improve computing performance since this eliminates transmitting data from memory subsystem to processing cores. There are two time frames when research on Near Data or Processing-In-Memory was explored. The first phase of the research was explored during 1990's and early 2000s. However, since it was not easy to integrate logic on the same die as memory devices, these efforts did not lead to practical implementations. More recently PIM research was revived with the advent of 3D stacked memory devices that contain a logic layer. Computing engines can be placed on the logic layer and separated from memory layers.

Related Publications

1. Charles Shelor, Krishna Kavi, "Reconfigurable Dataflow Graphs For Processing-In-Memory", IEEE 20th International Conference on Distributed Computing and Networking (ICDCN-2019), Bangaluru, India, Jan. 4-7, 2019.

2. C. Shelor and K. Kavi. "Dataflow based near data computing achieves excellent energy efficiency", International symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2017), Bochum, Germany, June 7-9, 2017.

3. M. Scrbak, et. al. "DVFS space exploration in power constrained processing-in-memory sysems", Proceedings of the 30th International conference on the Architecture of Computer Systems (ARCS 2017), April 3-6, 2017, Vienna, Austria.

4. M. Scrbak, M. Islam, K. Kavi, M. Ignatowski and N. Jayasena. "Exploring processing-in-memory design space", Journal of Systems Architecture (Elsevier), April 2017, pp 59-67, DOI: 10.1016/j.sysarch.2016.08.001.

5. Marko Scrbak, Mahzabeen Islam, Krishna Kavi, Mike Ignatowski, Nuwan Jayasena. "Processing-in-Memory: Exploring the design Space", 28th International Conference on the Architecture of Computer Systems (ARCS-2015), March 24-27, 2015, Porto, Portugal.

6. M. Islam, M. Scrback, K.M. Kavi, M. Ignatowski and N. Jayasena. "Improving node-level Map-Reduce performance using processing-in-memory technologies", 7th Workshop on UnConventional High Performance Computing (UCHPC2004), held in conjunction with the 20th European Conference Parallel Processing (EuroPar 2014), Porto, Portugal, Aug. 25-29, 2014.

Older Publications

M. Rezaei and K. Kavi. "ABT and SBT revisited: Efficient memory management techniques for object-oriented and web-based applications', in International Journal of Science and Technology, published by Scietia Irancia, Vol. 23, No. 3, pp 1217-1227, June 2016.

Wentong Li, Mehran Rezaei, Krishna Kavi, Afrin Naz and Philip Sweany. "Feasibility of decoupling memory management from the execution pipeline", Journal of Systems Architecture (published by Elsevier), Vol. 53, No. 12, pp 927-936, Dec. 2007

Wentong Li, Saraju Mohanty and Krishna Kavi. "Page-based software-hardware co-design of a dynamic memory allocator", the IEEE Computer Architecture Letters (available on line since July 2006).

M. Rezaei and K. M. Kavi. "Intelligent memory manager: Reducing cache pollution due to memory management functions" Journal of Systems Architecture, Vol. 52, No.1., pp 207-219 (Jan. 2006).

L.M. Fox, C.R. Hill, R.K. Cytron and K.M. Kavi. "Optimization of storage-referencing gestures" Proceedings of the Workshop on Compilers and Tools for Constrained Embedded Systems (CTES-2003), held in conjunction with Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES-2003), Oct. 29, 2003, San Jose, CA.

S. Donahue, M.P. Hampton, R. Cytron, M. Franklin and K.M. Kavi. "Hardware support for fast and bounded time storage allocation", Proceedings of the Workshop on Memory Processor Interfaces (WMPI), in conjunction with the International Symposium on Computer Architecture, May 2002, Anchorage, Alaska, pp