The memory subsystem of any computing system plays a significant role in the performance that can be achieved. The memory wall (access speed difference beetween processing elements and memory systems) is still an impediment to performance that can be delivered.
Heterogeneous Memory Architectures
9. Shashank Adavally, Mahzabeen Islam, Krishna Kavi. "Dynamically Adapting Page Migration Policies Based on Applications Memory Access Behaviors", accepted for publication in the ACM Journal of Emerging Technologies in Computing Systems.
8. Mahzabeen Islam, Shashank Adavally, Marko Scrbak, Krishna Kavi. "On-the-Fly Page Migration and Address Reconciliation for Heterogeneous Memory Systems", Accepted for publication in the ACM Journal on Emerging Technologies in Computing Systems (JETC).
7. Shashank Adavally and Krishna Kavi. "3D-DRAM performance for different OpenMP scheduling techniques in multicore systems", Proceedings of the 20th IEEE International Conference on High Performance Computing and Communications (HPCC-2018), Exeter, UK, June 28-30, 2018.
6. M. Islam, et, al. "3D-DRAM resident prefetching for heterogeneous memory systems", Proceedings of the 30th International conference on the Architecture of Computer Systems (ARCS 2017), April 3-6, 2017, Vienna, Austria
5. M. Islam, S. Banerjee, M. Meswani and K. Kavi. "Prefetching as a potentially effective technique for hybrid memory optimization", Proceedings of the International Symposium on Memory Systems (MEMSYS 16), October 3-6, 2016, Alexandria, VA.
4. K.M. Kavi, S. Pianelli, G. Pisano, G. Regina and M. Ignatowski. "Memory organizations for 3D-DRAM and PCMs in processor memory hierarchy", in the Elsevier Journal of Systems Architecture, Vol. 61, pp. 539-552, DOI: 10.1016/j.sysarc.2015.07.00, Aug. 2015.
3. K. Kavi, S. Pianelli, G. Pisano, G. Regina and M. Ignatowski. "3D DRAM and PCMs in Processor Memory Hierarchy", International Conference on Architecture of Computer Systems (ARCS 2014), pp 183-195, Feb 25-28, 2014, Luebeck, Germany.
2. J. Sherman, B. Potter, K. Kavi and M. Igantowski. "A multicore memory organization for 3D-DRAM as main memory", Proceedings of the 26th International conferernce the Architecture of Computer Systems (ARCS-2013), Prague, Czech Republic, Feb 19-22, 2013, pp 62-73.
1. A. Fawibe, J. Sherman, K. Kavi, M. Ignatowski and D. Mayhew. "New memory organizations for 3D DRAM and PCMs", Proceedings of the ARCS2012: Architecture of Computing Systems, TU Muenchen, Germany, Feb 28-March 02, 2012.
Cache Memory Optimizations
1. J. Shidal, A.J. Spilo, P. T. Scheid, R. Cytron and K. Kavi. "Recycling trash in cache", Proceedings of the International Symposium on Memory Management (ISMM-2015), June 14, 2015, Portland, OR.
2. C.F. Shelor, J. Buchanan, K. Kavi and R. Cytron. "Potential energy savings through eliminating unnecessary writes in the cache-memory hierarchy", International Journal of Computers and Their Applications (IJCA), Vol. 21, No. 3, Sept. 2014, pp 178-187
3. J. Shidal, Z. Gottlieb, R. Cytron, K. Kavi. "Trash in Cache: Detecting eternally silent stores", ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (MSPC-2014), June 13, 2014, Edinburgh, Scotland, Co-located with PLDI 2014.
4. C. Shelor, J. Buchanan and K. Kavi. "Quantifying wasted write energy in the memory hierarchy", International Conference on Computers And Their Applications (CATA-2014), Las Vegas, March 2014.
5. A. Naz and K. Kavi. "A smart cache design for embedded applications", International Journal of Advanced Research in Computer Sceince Jan-Feb. 2012, pp 46-51.
6. K. Kavi, I. Nwachukwu, A Fawibe . "A comparative analysis of performance improvement schemes for L-1 caches", Elsevier Journal of Computers and Electrical Engineering, March 2012, pp 243-257.
7. I. Nwachukwu, K. Kavi, A. Fawibe, C. Yan, "Evaluation of techniques to improve cache access uniformities", Proceedings of the 40th Annual Conference on Parallel Processing (ICPP-2011), pp 31-40, Taipei, Taiwan, Sept 13-16, 2011.
8. O. Adamo, A. Naz, K. Kavi, T. Janjusic and C.P.Chung. "Smaller split L-1 data caches for multi-core processing systems", Proceedings of IEEE 10th International Symposium on Pervasive Systems, Algorithms and Networks (I-SPAN 2009) to be held in Kao-Hsiung, Taiwan, December 14-16, 2009.
7. A. Naz, O. Adamo, K. Kavi and T. Janjusic. "Improving uniformity of cache access patterns using split data caches", Proceedings of ISCA PDCS-2009, Sept. 2009, Louisville, KY.
9. Afrin Naz, Krishna Kavi, JungHwan Oh and Pierofranco Foglia. "Reconfigurable split data caches: A novel scheme for embedded systems", Proceedings of the 22nd Annual ACM Symposium on Applied Computing, Seoul, Korea, March 11-15, 2007, pp 707-7112.
10. A. Naz, K. Kavi, W. Li and Philip Sweany. "Tiny split data caches make big performance impact for embedded applications", the Journal of Embedded Computing (Special Issue on Embedded Single-Chip Multi-core Architectures from System Design to Application Support), Vol.2, No.2, pp 207-219, November, 2006.