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Contact Information
or 3940 N. Elm Street, Suite F201, Denton, Texas 76207-7102
Voice: 940-565-4764; Fax: 940-565-2799
Publications
- Jee Ho Ryoo, Nagendra Gulur, Shuang Song, Lizy K. John: Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB. ISCA 2017: 469-480 [pdf]
- Yashwant Marathe, Nagendra Gulur, Jee Ho Ryoo, Shuang Song, Lizy K. John: CSALT: context switch aware large TLB. MICRO 2017: 449-462 [pdf]
- Jayvant Anantpur, Nagendra Dwarakanath Gulur, Shivaram Kalyanakrishnan, Shalabh Bhatnagar, R. Govindarajan: RLWS: A Reinforcement Learning based GPU Warp Scheduler. CoRR abs/1712.04303 (2017) [pdf]
- Nagendra Gulur, R. Govindarajan, Mahesh Mehendale: MicroRefresh: Minimizing Refresh Overhead in DRAM Caches. MEMSYS 2016: 350-361 [pdf]
- Nagendra Gulur, Narayanan L. Suriya: Understanding the Performance Benefit of Asynchronous Data Transfers in OpenCL Programs Executing on Media Processors. HiPC 2015: 135-144 [pdf]
- Nagendra Dwarakanath Gulur, Mahesh Mehendale, Ramaswamy Govindarajan: A Comprehensive Analytical Performance Model of DRAM Caches. ICPE 2015: 157-168 [pdf]
- Nagendra Dwarakanath Gulur, Mahesh Mehendale, R. Manikantan, R. Govindarajan:Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth. MICRO 2014: 38-50 [pdf]
- Nagendra Gulur, Mahesh Mehendale, Raman Manikantan, Ramaswamy Govindarajan: ANATOMY: an analytical model of memory system performance. SIGMETRICS 2014: 505-517 [pdf]
- Nagendra Dwarakanath Gulur, R. Manikantan, Mahesh Mehendale, R. Govindarajan: Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities. ICS 2012: 257-266 [pdf]
- Nagendra Dwarakanath Gulur, R. Manikantan, R. Govindarajan, Mahesh Mehendale: Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs. Poster at PACT 2011: 189-190
Puzzles
I look for new and interesting puzzles to collect and share. Here're some that we published in the CSE monthly newsletters.