Modern day processors have become much faster while memory speeds have lagged behind. As a result, memory accesses are one of the slowest operations a processor does. To combat this, processors now include multiple levels of caches in an effort to speed up accesses to frequently used data.
In multicore processors the last level cache in the cache hierarchy is next to main memory and is shared among multiple cores. Furthermore, in a traditional cache, each physical memory address is linearly mapped to a location in the cache, making it easy to predict the next address.
Side-channel attacks generally exploit known cache addresses and timing differences between data in the last level cache versus data that has been retrieved from main memory to steal data.
Several side-channel attacks such as Meltdown, Spectre, and Bernstein’s Attack have already been demonstrated that can successfully leak private data.
We introduce changes in the cache hardware architecture to avoid the information leakage due to Side-channel attacks. However, it can affect to the performance of the processor making it important to measure the impact of those changes.