Projects we are working on
Below we have summarized some of the projects we are currently working on. These include dataflow and multithreaded system, memory systems, and agent-oriented software engineering.
Dataflow and Multi-threaded Computer Architecture
We have been investigating hybrid dataflow—von Neumann architectures for multithreaded systems. We have investigated the use of instruction, data, and I-structure cache memories with ETS dataflow.
We are currently developing a new dataflow known as Scheduled Dataflow (SDF) that executes instructions synchronously.
We are working on various compile-time optimizations with the SDF, including operand memory reuse, inplace updates for I-structure memories, split phase and non-split phase I-structure accesses, speculative pre-loading of thread contexts, predicated instructions. Each PE in our SDF contains at least one unit for processing memory accesses (called SPs) and at least one unit for executing operations (called EPs). Our SPs and EPs are very simple, in order execution pipelines.
We are also exploring how our SDF can be configured into scalable, clusters, with each cluster containing a small number of SPs and EPs.
Most recently we are exploring Thread Level Speculation within the context of our SDF.
We have developed a formal model based on dataflow graphs that can be used for the specification and analysis of concurrent processing systems.
Uninterpreted dataflow graphs and stochastic dataflow graphs are isomorphic to Petri nets. We have developed the necessary formalisms to prove the isomorphism and also developed analysis techniques for directly analyzing stochastic dataflow graphs. We have developed approximation techniques for analysis using graph reductions and "nearly" completely decomposable Markov processes. We have also developed formal theory based on first-order logic for the purpose of verifying logical specification of systems using our dataflow graphs.
Learn more about SDF on our Scheduled Dataflow page.
Hardware-Software Co-Design
We are developing a compiler that converts C-code into a general-purpose CPU code and FPGA code based upon a hardware specification and performance requirements.
Intelligent Memories and Memory Management
In this research we are investigating the use of separate hardware devices for the purpose of off-loading some functions from CPU.
We are also looking at optimizing cache memories for embedded systems. One idea we have been exploring is the use of separate data caches at Level 1, so that different types of data can be cached in different regions. It is then possible to explore reconfigurable designs whereby cache can be configured to specific applications to improve performance and reduce energy consumed while executing the applications.
More specifically we are looking to off-load memory management functions including memory allocation/deallocation, garbage collection, jump pointers and address forwarding functions to the logic on memory chips available with IRAM and PIM devices.
Our initial studies have concerntrated on the impact of off-loading memory allocation functions on the CPU cache performance, since the allocation functions will no longer pollute the CPU cache.
In this research we are also studying various allocator and garbage collection techniques that are suitable for execution by a dedicated hardware unit.
Agent-Oriented Software Engineering
In this reseach we are investigating formal and systematic design and analysis methods for the development of robust, adaptive agent-based software systems.
Our goal is to bring together traditional formal methods for specification and verification of functional properties with stochastic techniques to model dynamic adaptibility of agent software designs.